Name

 

GIRAY KOMURCU

Address

 

Tatlısu Mah. Şanlı Cad.       

Palmiye Apt. No:51/9 Ümraniye

Istanbul/TURKEY

GSM

 

+90 532 706 6449

E-mail

 

giraykomurcu@gmail.com

Nationality

 

Turkish

Date of birth

 

13 November 1982

               

 

 

 

Employment Experience

 

               

• Dates

 

August 2005 – Present

• Name and address of the employer

 

TUBITAK – UEKAE – YITAL (The Scientific and Technological Research Council of Turkey - The National Institute of Electronics and Cryptology -  Semiconductor Technologies Research Laboratory), Gebze Kocaeli Turkey

 

• Occupation or positions held

 

Chief Researcher – ASIC Design Engineer (September 2013 – present)

Senior Researcher – ASIC Design Engineer (September 2008 – 2013)

Researcher – ASIC Design Engineer (August 2005 – September 2008)

 

• Main activities and responsibilities

 

-        Preparing the project plan and budget for new projects

-        Designing an HF RFID tag (13.56 MHz) with symmetric authentication according to ISO 14443-A from defining the specs to tape-out (0.18 µm).

-        Full hardware implementation of DES and DES3 resistant to Side Channel Analysis (SCA) and participating in the system level design of Secure Smart Card design project (0.25µm, 0.18 µm, 0.13 µm).

-        Performing SCA on Smart Card for testing the SCA resistance and developing enhanced security countermeasures.

-        Writing drivers for coprocessors in Smart Card using Assembly Language.

-        Developing test environment and algorithms in Matlab to be used in Smart Card design process.

-        Implementation of cryptographic algorithms for information security devices,

-        Prototyping and testing on FPGA boards.

-        VLSI front-end flow; RTL coding in VHDL, simulation and functional verification, synthesis, timing Analysis.

-        VLSI back-end flow; custom layout generation by automatic place & route tools, full-custom layout, physical verification, extraction, gate level simulation, transistor level post layout simulation.

-        Developing automatic place & route scripts for MAGMA tools.

-        Verification and testing of Smart Card Operating System.

 

 

• Dates

 

June 2004 – August 2004

• Name and address of the employer

 

Cypress Semiconductor Istanbul Technology Center, Turkey.

• Occupation or position held

 

Intern

• Main activities and responsibilities

 

-         Feasibility study of Chip Level jitter simulation for FTG (Frequency Timing Generator)

-         Products and creation of .lib files as a part of Intellectual Property  Process.

 

 

Educational Background

 

• Dates

 

2008 - 2014

• Name of the institute

 

Boğaziçi University, Istanbul, Turkey

Faculty of Engineering, Electrical & Electronics Engineering PhD Program

• Thesis subject

 

• Title of qualification awarded

 

Realization and Analysis of High Performance Physical Unclonable Functions Based on Ring Oscillators

PhD

• GPA

 

3.50 / 4.00

 

• Dates

 

2005 – 2007

• Name of the organization

 

Boğaziçi University, Istanbul, Turkey

Faculty of Engineering, Electrical & Electronics Engineering MSc. Program

•Thesis subject

 

An Efficient Hardware Implementation of the Tate Pairing in Characteristic Three Elliptic Curve Crypto Algorithm

• Title of qualification awarded

 

MSc.

• GPA

 

3.50 / 4.00

 

 

 

• Dates

 

2000 – 2005

• Name of the organization

 

Sabancı University, Istanbul, Turkey

Microelectronics Engineering, Faculty of Engineering and Natural Sciences (FENS)

•Thesis subject

 

Design and Implementation of a System Management Bus (SMBus) Controller Hardware

• Title of qualification awarded

 

BSc.

• GPA

 

3.61 / 4.00

 

• Dates

 

 

1997-2000

• Name of the organization

• GPA

 

 

Atatürk Science School, Istanbul, Turkey

4.86 / 5.00

 

 

Ranked 258th, Science-Math among 1.5million students at the university entrance exam.

 

Courses Taught

 

 

 

 

BGM 506, Güvenli İmplementasyon ve Yan Kanal Analizi, İstanbul Şehir University, Spring 2015.

 

 

Trainings

 

 

 

Synopsys Design Tools

15-19 December 2014, Organized by UEKAE, TUBITAK, Conducted by Synopsys.

 

Magma Design Tools

13-17 May 2013, Organized by UEKAE, TUBITAK, Conducted by Magma.

 

Signal Integrity and Board Design

13-15 December 2009, Organized by UEKAE, TUBITAK, Conducted by Xilinx.

 

Reverse Engineering

3-7 December 2007, Organized by UEKAE, TUBITAK, Conducted by SiVenture, UK.

 

 

 

Active and Passive Side Channel Analysis

5-9 November 2007, Organized by UEKAE, TUBITAK, Conducted by SiVenture, UK.

 

 

 

Advanced VLSI Design 5-9 September 2007, EPFL (Ecole Polytechnique Federal de Lausanne), Lausanne Switzerland.

 

 

Technical Skills

And Competences

 

 

 

IC design skills

 

 

• Design environment

 

Cadence

• Design tools

 

Virtuoso (Layout and Schematic editor)

Diva, Assura, Dracula, Hercules, StarRC (Verification and extraction)

RTL Compiler(HDL synthesis)

First Encounter, Design Compiler, Talus (Place and Route)

•Simulators

 

Hspice, Spectre, Nanosim, Finesim.

• Hardware Description Languages

 

VHDL and Verilog.

•Design tools for FPGA programming

 

Xilinx ISE (HDL compiler), Modelsim (Simulator)

 

Computer skills

 

 

• Operating systems

 

Windows, MS-DOS, Linux, Unix, Solaris.

• Software

 

Matlab, Pspice.

• Programming languages

 

C,C++, Assembly.

 

 

PUBLICATIONS

 

 

 

 

 

 

Komurcu G. and A. E. Pusane and G. Dundar, "Enhanced Challenge-Response
Set and Secure Usage Scenarios for Ordering Based RO-PUFs", IET-Circuits,
Devices, and Systems, (IET-CDS), accepted for publication, 2014.

Komurcu G. and A. E. Pusane and G. Dundar, "An Efficient Grouping Method and Error Probability Analysis for RO-PUFs", Computers & Security, vol.49, pp.123-131, 2015.

Komurcu G. and A. E. Pusane and G. Dundar, "Effects of Aging and Compensation Mechanisms in Ordering Based RO-PUFs", Integration the VLSI Journal, revisions are requested, 2014.

Komurcu G. and A. E. Pusane and G. Dundar, "A Ring Oscillator Based PUF
Implementation on FPGA", IU-Journal of Electrical and Electronics Engineering,
(IU-JEEE), vol.13, no. 2, pp. 1647-1652, 2012.

 

Komurcu G. and E. Savas, "An Efficient Hardware Implementatioın of Tate Pairing in Characteristic Three" - Third International Conference on Systems, (ICONS), 2008

Komurcu G. and G. Dundar, "Determining the Quality Metrics for PUFs and
Performance Evaluation of Two RO-PUFs", IEEE 10th International New Circuits
and Systems Conference, (NEWCAS), pp. 73-76, 2012.

Komurcu G. and A. E. Pusane and G. Dundar, "FPGA Uzerinde Ring Osilatörü
Tabanlı PUF Gerçeklemesi", Elektrik - Elektronik, Bilgisayar ve Biyomedikal
Mühendisliği Sempozyumu, (ELECO), 2012.

Komurcu G. and A. E. Pusane and G. Dundar, "Dynamic Programming Based
Grouping Method for RO-PUFs", 9th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), pp. 329-332, 2013.

Komurcu G. and A. E. Pusane and G. Dundar, "Analysis of Ring Oscillator
Structures to Develop a Design Methodology for RO-PUF Circuits", IEEE 21st
International Conference on Very Large Scale Integration (VLSI-SoC), pp. 332-
335, 2013.

Komurcu G. and A. E. Pusane and G. Dundar, "Robust RO-PUFs with Enhanced
Challenge-Response Set", Electrical Engineering/Electronics, Computer,
Telecommunications and Information Technology Conference (ECTI-CON), 2014.

Komurcu G. and A. E. Pusane and G. Dundar, "Konvansiyonel ve Sıralama Tabanlı RO-PUF'ların Uygulanması ve Karşılaştırılması" 3rd  International Symposium on Digital Forensics and Security (ISDFS), 2015.

 

Komurcu G. and A. E. Pusane and G. Dundar, "Implementation and Comparison of Conventional and Ordering Based RO-PUFs for Secret Key Generation" 8th International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS), 2015.

 

Language Skills

 

ENGLISH  - Advanced (TOEFL: 270/300; KPDS:90/100)

 

        Interests            Mountaineering & Rock Climbing, Camping, Photography,